The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of ZVS Synchronous Buck Converter

This work is about the analysis of dead time variation on switching losses in a Zero Voltage Switching (ZVS) synchronous buck converter (SBC) circuit. In high frequency converter circuits, switching losses are commonly linked with high and low side switches of SBC circuit. They are activated externally by the gate driver circuit. The duty ratio, dead time and resonant inductor are the parameters that affect the efficiency of the circuit. These variables can be adjusted for the optimization purposes. The study primarily focuses on varying the settings of input pulses of the MOSFETs in the resonant gate driver circuit which consequently affects the performance of the ZVS synchronous buck converter circuit. Using the predetermined inductor of 9 nH, the frequency is maintained at 1 MHz for each cycle transition. The switching loss graph is obtained and switching losses for both S1 and S2 are calculated and compared to the findings from previous work. It has shown a decrease in losses by 13.8 % in S1. A dead time of 15 ns has been determined to be optimized value in the SBC design. Keywords— PSpice Simulation, Resonant Gate Driver, Synchronous Buck Converter, Switching Losses